PD672X/30/32/33 — ZV Port
Implementation
Application Note
May 2001
As of May 2001, this document replaces the Basis Communications Corp. document AN-PD10.
PD672X/30/32/33 — ZV Port Implementation
Contents
Introduction..................................................................................................................5
Overview........................................................................................................................6
Zoomed Video (ZV)....................................................................................................6
A Typical ZV Port Implementation ......................................................................6
Layout Guidelines....................................................................................................15
Figures
Typical ZV Port Implementation ............................................................................7
Buffer Implementation for Audio DAC .................................................................10
Tables
Application Note
3
PD672X/30/32/33 — ZV Port Implementation
4
Application Note
PD672X/30/32/33 — ZV Port Implementation
1.0
Introduction
The PD6710, PD6722, and PD6729 are single-chip PCMCIA interface controllers capable of
controlling one or two PCMCIA or compact Flash sockets, respectively. They are designed for use
in embedded applications and notebook systems where reduced form factor and low power
consumption are critical design objectives.
Current typical application examples include:
■ Routers
■ Integrated access devices
■ DSLAMs
■ Access network servers
■ PBXs
■ Terminal servers
■ Vending machines
■ Portable handheld systems
■ Data acquisition systems
■ Settop boxes
■ Point of Sale terminals
■ Navigation systems
■ Measurement equipment
With the PD6710, a complete single-socket PCMCIA solution with power-control circuitry can
occupy less than 1.5 square inches (10 square centimeters) of board space. Similarly, with the
PD6722 and PD6729, a complete dual-socket PCMCIA solution with power-control circuitry can
occupy less than 2 square inches (13 square centimeters) of board space.
The PD67XX controllers are completely compatible with the standards of PCMCIA (Personal
Card Memory International Association) Release 2.0 Standard as well as JEIDA (Japan Electronic
Industry Development Association) Version 4.1 Standard (PD6729 is compliant with the PCI 2.1
Specification. The PD67XX controllers also offer special power-saving features such as Automatic
Low-power Dynamic Mode and Suspend Mode. Both controllers are true mixed-voltage devices
that can operate at +5 volts, +3.3 volts, or a combination of these at various interfaces. The
controllers have full internal buffering and require no additional circuitry to interface to the ISA (or
ISA-like) Bus for the PD6710 and PD6722, and the PCI Bus for PD6729, or to PCMCIA sockets.
Note: In this document, PD67XX represents the PD6710, PD6722, and PD6729.
Application Note
5
PD672X/30/32/33 — ZV Port Implementation
2.0
Overview
This application note discusses system design considerations associated with the implementation
of the ZV (Zoomed Video) Port when using the PD6722/’29/’30, or PD6832 controller devices.
Intended to assist the system designer, this document highlights how various aspects of the PC
Card relate to the ZV Port implementation. Since the ZV Port implementation overlaps PC Card,
graphics, and audio technologies, consulting with appropriate applications/product groups is
recommended.
3.0
4.0
Zoomed Video (ZV)
ZV is a cost-effective method of accessing live video through a PC Card. The ZV Port provides a
direct connection between a PC Card and a VGA controller and an audio DAC. It allows the PC
Card to directly write video data to an input port of a graphics controller and audio data to a digital-
to-analog converter. Intel offers a family of PC Card (PCMCIA) Controllers that support the ZV
Port standard.
A Typical ZV Port Implementation
Figure 1 on page 7 illustrates a typical ZV Port implementation with PD6722/’29/’30 and PD6832
controller devices. These devices support the ZV Port in the ‘bypass’ mode during which the
signals are directly rerouted from the PC Card bus to the Video ZV Port (the video port of the
GD7XXX device is also referred to as the V-Port). This rerouting is accomplished by tristating
specific PC Card Bus signals from the PC Card (PCMCIA) Controller. Once these signals are
tristated by the host controller during the ZV Port operation, the ZV Port-compliant PC Card drives
video and audio data on the same signals. Video signals from the PC Card are routed to the ZV
Port-capable video controller; audio signals from the PC Card are routed to the ZV Port-compliant
audio DAC in the host system. This mechanism provides an inexpensive means of adding video/
audio capability to a notebook or desktop system without any additional burden on the host bus.
As specified in the PC Card standard, a ZV Port-compliant PC Card, when inserted into a PC Card
slot, is initialized the same way as a PC Card 16. It is then recognized as a ZV Port card and
enters the ZV Port mode by tristating address pins A[25:4] of the PC Card bus when the
Multimedia Enable bit (bit 0 of the Misc. Control register 1 at index 16h in the PD6722/’29/’30 and
PD6832; in the PD6832 it can also be at memory offset 816h) is set. These address pins are outputs
from the PD6722/’29/’30/’6832 during normal PC Card operation. The tristating of the address
pins by the adapter allows the A[25:4] signals to simultaneously carry video data and video capture
timing control signals directly to a video controller, and the audio signals to the audio DAC. The
PD6832 has a Multimedia Arm bit (bit 7 of the Misc. Control register 3; this register is at I/O index
2Fh, extended index 25h, or memory offset 925h) that works as the overriding control bit. Until the
Multimedia Arm bit is set, the Multimedia Enable bit does not tristate the address bit as previously
described. When the Multimedia Expand bit (bit 6 of Misc. Control register 3) is set to ‘1’, CE2
and D[15:8] are tristated on the 16-bit PC Card bus, in addition to the tristating of the address
signals A[25:4]. The Multimedia Expand bus allows 24-bit video from the ZV Port-compliant PC
Card.
6
Application Note
PD672X/30/32/33 — ZV Port Implementation
Note that ZV Port implementation is likely to vary depending on the platform; the Socket Services
software must be customized to address these variances. Controlling the OE (output enable) inputs
of the external buffers depends upon specific hardware design and software needs to be aware of
specifics, such as the I/O Port addresses.
When the PC Card Multimedia mode is used, Intel recommends that the ZV Port pins be connected
as shown in Tables 1–3 for the various controller devices. The pin assignments provided in the
tables ensure signal integrity and compliance with the ZV Port standard. By disabling or powering
down the ZV Port, this connection between the GD7XXX and the PC Card bus does not interfere
with the normal (non-multimedia) PC Card bus operation.
When the ZV Port is disabled, VPM (Video Port Manager) software or other client drivers must
program the VGA controller so as not to adversely affect the video port of the VGA controller. A
bus switch, turned off during normal PC Card bus operation, may be needed to reduce the load on
the PC Card bus.
Figure 1. Typical ZV Port Implementation
TV
LCD
CRT
SPEAKERS
DRAM
ANALOG
ENCODER
AMP
AUDIO
CODEC
GD7XXX
4
PCM
AUDIO
INPUT
19
4
AUDIO
PCM
CONVERTER
ZV PORT
(Video)
AUDIO
VIDEO
PD6722
PD6729
PD6730
PD6832
PD6833
PC CARD
VIDEO
DECODER
INTERFACE
NTSC/PAL
RF SIGNAL
19
VIDEO & CONTROL
PC CARD
MOTHERBOARD
Application Note
7
PD672X/30/32/33 — ZV Port Implementation
A buffer circuit placed between the PC Card bus and the VGA video port reduces the trace length
to lower the loading effect. The ZV Port standard requires that the length of the trace between the
PC Card connector and the buffer (if used) must be less than two inches. Buffers are also needed to
support ZV Port PC Cards in either socket.
In a full implementation of the ZV Port, multiple PC Card slots can be used to implement the ZV
Port. This implies that the user inserts the multimedia PC Card into either slot and the system is
able to recognize and respond to this event appropriately. To allow the multimedia PC Card to be
inserted into either slot, the individual PC Card bus must be isolated from the other bus by using
buffers in the system. The following block diagrams illustrate possible ZV Port implementations.
Note that the control signal inputs to the buffers can be controlled by different methods. For the
GD7XXX, the buffer control comes from the I/O pins of the GD7XXX that are labeled VPCNTL
and TVON. For further information, refer to the application note titled, “V-Port Implementation for
the GD7548 Super VGA Controller”.
8
Application Note
PD672X/30/32/33 — ZV Port Implementation
5.0
Dedicated Socket Approach to ZV Port
Implementation
VGA controller to support a single dedicated ZV Port slot. This simple implementation does not
require any external buffer or glue logic; the only limitation is that one socket must be dedicated to
the ZV Port. Also, depending upon the audio controller used, a buffer may be required between the
PC Card bus and the audio controller. The designer must ensure that while in R2 PC Card mode
(non-ZV operation), the traffic over the bus does not cause the audio input to be driven or the video
port of the VGA controller to be adversely affected. If the audio controller or VGA controller do
on page 15 to determine if buffers are required for the video path.
Figure 2. Dedicated Socket Approach to ZV Port Implementation
GD7XXX
V-PORT
AUDIO CODEC
PD6722
PD6729
ZV PORT PC CARD
PC CARD BUS
PD6730
PD6832
PD6833
Application Note
9
PD672X/30/32/33 — ZV Port Implementation
6.0
Buffer Implementation for Audio DAC
A buffer solution to isolate the audio controller when the socket is not configured in ZV Port mode
is shown in Figure 3. This illustrates how to control the buffer enable; if the GD7XXX is used, then
one of the GPO pins can control the buffer enable.
Figure 3. Buffer Implementation for Audio DAC
GD7XXX
V-PORT
PD6722
PD6729
PD6730
PD6832
PD6833
ZV PORT PC CARD
PC CARD BUS
OE
BUFFER
AUDIO
10
Application Note
PD672X/30/32/33 — ZV Port Implementation
7.0
ZV Port Implementation for Socket A and B
Figure 4 shows the ZV Port support for socket A and B. If using the GD7XXX, two of the GPO
pins can control the buffer output enables. Since there is only one V-Port, a ZV Port PC Card can
be inserted in either Socket A or Socket B.
Figure 4. ZV Port Implementation for Socket A and B
TVON
VPCNTL
GD7XXX
GLUE LOGIC
2 NAND GATES
1 INVERTER
V-PORT
AUDIO
OE
OE
BUFFER
BUFFER
Z
SOCKET A
R
PD6722
PD6729
PD6730
PD6832
PD6833
PC CARD BUS A
PC CARD BUS B
P
ZV PORT PC CARD
X
SOCKET B
ZV PORT PC CARD
Table 1. PC Card, ZV Port, and PD6722 Pin Assignment (Sheet 1 of 2)
PC Card
Pin
Number
I/O in PC
Card
Mode
PC Card
Pin
ZV Port Pin
Name
I/O in ZV
Port Mode
PD6722S
ocket A
PD6722S
ocket B
Comments
8
A10
A11
A9
I
I
I
I
I
I
HREF
VSYNC
Y0
O
O
O
O
O
O
21
25
28
30
33
35
85
89
91
93
95
97
Horizontal sync to ZV Port
Vertical sync to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
10
11
12
13
14
A8
Y2
A13
A14
Y4
Y6
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
Application Note
11
PD672X/30/32/33 — ZV Port Implementation
Table 1. PC Card, ZV Port, and PD6722 Pin Assignment (Sheet 2 of 2)
PC Card
Pin
Number
I/O in PC
Card
Mode
PC Card
Pin
ZV Port Pin
Name
I/O in ZV
Port Mode
PD6722S
ocket A
PD6722S
ocket B
Comments
19
20
21
22
23
A16
A15
A12
A7
I
I
I
I
I
UV2
UV4
O
O
O
I
41
43
45
47
49
103
105
107
109
112
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Audio SCLK PCM signal
Audio MCLK PCM signal
UV6
SCLK
MCLK
A6
I
Tristated by Controller; no
connection in PC Card
24–25
26–29
A[5:4]
A[3:0]
I
I
RESERVED
RFU
I
50,53
113,115
55,57,58,6
0
118,120, Used for accessing PC
ADDRESS[3:0]
121,123
131
94
Card
33
46
47
48
49
50
53
54
55
56
60
62
IOIS16#
A17
O
I
PCLK
Y1
O
O
O
O
O
O
O
O
O
O
O
O
68
32
34
36
38
40
42
44
46
48
56
59
Pixel clock to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Audio LRCLK PCM signal
Audio PCM Data signal
A18
I
Y3
96
A19
I
Y5
98
A20
I
Y7
100
102
104
106
108
110
119
122
A21
I
UV0
UV1
UV3
UV5
UV7
LRCLK
SDATA
A22
I
A23
I
A24
I
A25
I
INPACK#
SPKR#
O
O
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
Table 2. PC Card, ZV Port, and PD6729 Pin Assignment (Sheet 1 of 2)
PC Card
Pin
Number
I/O in PC
Card
Mode
PC Card
Pin
ZV Port Pin
Name
I/O in ZV
Port Mode
PD6729S PD6729S
Comments
ocket A
ocket B
8
A10
A11
A9
I
I
I
I
I
I
I
I
HREF
VSYNC
Y0
O
O
O
O
O
O
O
O
77
82
84
86
88
90
97
99
153
157
159
162
164
166
172
174
Horizontal sync to ZV Port
Vertical sync to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
10
11
12
13
14
19
20
A8
Y2
A13
A14
A16
A15
Y4
Y6
UV2
UV4
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
12
Application Note
PD672X/30/32/33 — ZV Port Implementation
Table 2. PC Card, ZV Port, and PD6729 Pin Assignment (Sheet 2 of 2)
PC Card
Pin
Number
I/O in PC
Card
Mode
PC Card
Pin
ZV Port Pin
Name
I/O in ZV
Port Mode
PD6729S PD6729S
Comments
ocket A
ocket B
21
22
23
A12
A7
I
I
I
UV6
SCLK
MCLK
O
I
101
104
106
176
179
181
Video data to ZV Port
Audio SCLK PCM signal
Audio MCLK PCM signal
A6
I
Tristated by Controller; no
connection in PC Card
24–25
26–29
A[5:4]
A[3:0]
I
I
RESERVED
RFU
I
108, 110
183, 185
112, 114,
115, 117
187,190, Used for accessing PC
191, 193 Card
ADDRESS[3:0]
33
46
47
48
49
50
53
54
55
56
60
62
IOIS16#
A17
O
I
PCLK
Y1
O
O
O
O
O
O
O
O
O
O
O
O
125
87
201
163
165
167
169
171
173
175
178
180
189
192
Pixel clock to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Audio LRCLK PCM signal
Audio PCM data signal
A18
I
Y3
89
A19
I
Y5
92
A20
I
Y7
94
A21
I
UV0
UV1
UV3
UV5
UV7
LRCLK
SDATA
96
A22
I
98
A23
I
100
103
105
113
116
A24
I
A25
I
INPACK#
SPKR#
O
O
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
Table 3. PC Card, ZV Port, and PD6730/’6832 Pin Assignment (Sheet 1 of 2)
I/O in PC
Card
Mode
PD6730 or
PD6832
Socket A
PD6730 or
PD6832
Socket B
PC Card
Pin No.
PC Card
Pin
ZV Port Pin
Name
I/O in ZV
Port Mode
Comments
8
A10
A11
A9
I
I
I
I
I
I
I
I
I
I
HREF
VSYNC
Y0
O
O
O
O
O
O
O
O
O
I
73
77
80
82
84
86
93
95
97
100
149
153
155
157
159
162
169
171
173
175
Horizontal sync to ZV Port
Vertical sync to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Audio SCLK PCM signal
10
11
12
13
14
19
20
21
22
A8
Y2
A13
A14
A16
A15
A12
A7
Y4
Y6
UV2
UV4
UV6
SCLK
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
Application Note
13
PD672X/30/32/33 — ZV Port Implementation
Table 3. PC Card, ZV Port, and PD6730/’6832 Pin Assignment (Sheet 2 of 2)
I/O in PC
Card
Mode
PD6730 or
PD6832
Socket A
PD6730 or
PD6832
Socket B
PC Card
Pin No.
PC Card
Pin
ZV Port Pin
Name
I/O in ZV
Port Mode
Comments
23
A6
I
I
MCLK
I
103
178
Audio MCLK PCM signal
Tristated by Controller; no
connection in PC Card
24–25
A[5:4]
RESERVED
RFU
105, 107
181, 183
ADDRESS
[3:0]
109,111,
113,116
185,187,
189, 191
26–29
A[3:0]
I
I
Used for accessing PC Card
33
46
47
48
49
50
53
54
55
56
60
62
IOIS16#
A17
O
I
PCLK
Y1
O
O
O
O
O
O
O
O
O
O
O
O
125
83
201
158
161
164
166
168
170
172
174
176
186
190
Pixel clock to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Audio LRCLK PCM signal
Audio PCM Data signal
A18
I
Y3
85
A19
I
Y5
88
A20
I
Y7
90
A21
I
UV0
UV1
UV3
UV5
UV7
LRCLK
SDATA
92
A22
I
94
A23
I
96
A24
I
99
A25
I
102
110
114
INPACK#
SPKR#
O
O
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
14
Application Note
PD672X/30/32/33 — ZV Port Implementation
8.0
Layout Guidelines
The VGA controller, the PC Card (PCMCIA) Controller, and the PC Card Sockets must be in close
proximity to one another. This requirement is particularly important when the PD6832 or PD6833
device is used along with the ZV Port for Card bus implementation. According to tests conducted
by PCMCIA ZV Port subcommittee, the stubs to the GD7548 device or any other VGA controller
between points P and R for PC Card bus A and between points X and Z for PC Card bus B. Vias
have already been included in this recommended stub length.
• Maximum total capacitive loading for each Card bus signal = 22 pF
• Maximum input capacitance of each host controller pin = 10 pF
• Maximum input capacitance of the buffer pin = 5 pF
A total of 7 pF remains for the PC Card connector-to-buffer input pin trace. A maximum trace
length of two inches satisfies CardBus requirements.
System designers must check the VCC bounce, ground bounce, and crosstalk on CardBus/ZV Port
prototypes to ensure that the effect is minimal. The CCLK signal on the CardBus must be thick
with sufficient gap from adjacent traces and series termination must be used. Guidelines for CCLK
signal are included in the latest PC Card specifications.
Note: Intel recommends that designers contact the PCMCIA organization for the latest revision of the ZV
Port standard.
Application Note
15
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